Details
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Type:
Improvement
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Status:
Closed
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Priority:
Major
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Resolution: Fixed
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Affects Version/s: None
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Fix Version/s: 2.9.3
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Component/s: Compiler: Baseline, Instruction Architecture: Intel
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Labels:None
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Number of attachments :
Description
In some situations we generate a displacement of 0 in the baseline compiler. For example, if we have 1 local then iload0 becomes "push [ESP+0]" when the operand stack is empty. Encoding this is RegDisp form creates an instruction of
opcode = 0xFF
modrm = 01b || 110b || 100b
(include /6 of the extended part of the opcode)
sib = 00100100b
imm8 = 0
ie. 4 bytes long. If this were RegInd form then the instruction could be:
opcode = 0xFF
modrm = 00b || 110b || 100b
sib = 00100100b
ie. 3 bytes long. We probably don't want to clutter up the assembler with "if (disp == 0) ..." so we should fix the baseline compiler.
Activity
I think it is sane (Intel manual in hand) but there's a problem that we don't handle ESP with an SIB byte for RegInd instructions. That should probably be put in as a bug 
off the top of my head (don't have the IA32 instruction manual handy) I think it's pretty likely we do this because the RegInd mode can't be used with ESP as a base register. There are a bunch of funny exceptions about addressing modes using ESP as the base that forced us to do weird things in the assembler.