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Key: RVM-387
Type: Improvement Improvement
Status: Closed Closed
Resolution: Fixed
Priority: Major Major
Assignee: Unassigned
Reporter: Ian Rogers
Votes: 0
Watchers: 0
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RVM

Baseline compiler emits RegDisp instructions when the Disp is 0

Created: 05/Mar/08 10:29 AM   Updated: 07/Mar/08 03:25 AM
Component/s: Compiler: Baseline, Instruction Architecture: Intel
Affects Version/s: None
Fix Version/s: 2.9.3

Time Tracking:
Not Specified


 Description  « Hide
In some situations we generate a displacement of 0 in the baseline compiler. For example, if we have 1 local then iload0 becomes "push [ESP+0]" when the operand stack is empty. Encoding this is RegDisp form creates an instruction of
opcode = 0xFF
modrm = 01b || 110b || 100b
(include /6 of the extended part of the opcode)
sib = 00100100b
imm8 = 0
ie. 4 bytes long. If this were RegInd form then the instruction could be:
opcode = 0xFF
modrm = 00b || 110b || 100b
sib = 00100100b
ie. 3 bytes long. We probably don't want to clutter up the assembler with "if (disp == 0) ..." so we should fix the baseline compiler.

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David Grove added a comment - 05/Mar/08 10:37 AM
off the top of my head (don't have the IA32 instruction manual handy) I think it's pretty likely we do this because the RegInd mode can't be used with ESP as a base register. There are a bunch of funny exceptions about addressing modes using ESP as the base that forced us to do weird things in the assembler.

Ian Rogers added a comment - 05/Mar/08 10:39 AM
I think it is sane (Intel manual in hand) but there's a problem that we don't handle ESP with an SIB byte for RegInd instructions. That should probably be put in as a bug

Ian Rogers added a comment - 05/Mar/08 10:43 AM
I'm wrong, we do handle the SIB byte for ESP properly for indirects.

Ian Rogers added a comment - 06/Mar/08 08:50 AM
Patch in r14002.

Ian Rogers added a comment - 07/Mar/08 03:25 AM
Performance looks unchanged but code size should be fractionally better. Closing issue.