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Key: RVM-202
Type: Improvement Improvement
Status: Open Open
Priority: Minor Minor
Assignee: Unassigned
Reporter: Ian Rogers
Votes: 0
Watchers: 0
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RVM

Reorgnanize SSE code generation to be based on SSE version

Created: 01/Sep/07 07:47 AM   Updated: 11/Apr/08 09:29 AM
Component/s: Compiler: Baseline, Compiler: Optimizing, Instruction Architecture: Intel
Affects Version/s: None
Fix Version/s: 1000

Time Tracking:
Not Specified


 Description  « Hide
AMD have announced SSE5 with new compare instructions that should allow us to more easily match Java's semantics:

http://developer.amd.com/assets/sse5_43479_BDAPMU_3-00_8-27-07.pdf

I think this makes it more the case that we want to stage the instructions generated for SSE based on the version number.

SSE=0 => use x87 fcomi
SSE=1 or 2 => use comiss for single and fcomi for doubles
SSE=3 or 4 => use comiss and comisd
SSE=5 => use comss and comsd



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