RVM

SSE rules for memory operands, conditional moves, etc.

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Currently SSE rules just perform FP math using registers and not memory operands. We should have memory operand rules mirroring those for integer IA32 instructions. We should also look at issues such as conditional moves. The current support for floating point conditional moves is based on what the x87 supports. SSE introduces new instructions which we should possibly adapt the branch optimizations to target.

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is duplicated by

Improvement - An improvement or enhancement to an existing feature or task. RVM-359 Introduce two non-terminals called float_load and double_load, and impove the SSE2's add, sub, mul, div rules with the two terminals. The cost of the original add,sub,mul, div rules was changed to match the description of the BURS file.

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Ian Rogers added a comment -

The AMD64 optimization guide recomends:

Use the MOVLPS and MOVLPD instructions to move scalar floating-point data into the XMM registers prior to addition, multiplication, or other scalar instructions.

this is because it avoids clearing the upper 64 or 96 bits of the register. Currentyly we use MOVSS and MOVSD.

http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25112.PDF page 212

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Ian Rogers added a comment - The AMD64 optimization guide recomends: Use the MOVLPS and MOVLPD instructions to move scalar floating-point data into the XMM registers prior to addition, multiplication, or other scalar instructions. this is because it avoids clearing the upper 64 or 96 bits of the register. Currentyly we use MOVSS and MOVSD. http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25112.PDF page 212
Ian Rogers made changes -
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Link This issue is duplicated by RVM-359 [ RVM-359 ]
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Ian Rogers added a comment -

Fixed in r13942. MOVSD is switched to MOVLPD when the operands are register and memory. MOVSS isn't switched to MOVLPS (although AMD recommend this) as we don't guarantee 8byte alignment of floats (we could) and MOVLPS could access beyond a page boundary causing an unexpected page fault.

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Ian Rogers added a comment - Fixed in r13942. MOVSD is switched to MOVLPD when the operands are register and memory. MOVSS isn't switched to MOVLPS (although AMD recommend this) as we don't guarantee 8byte alignment of floats (we could) and MOVLPS could access beyond a page boundary causing an unexpected page fault.
Ian Rogers made changes -
Assignee Ian Rogers [ ianrogers ]
Resolution Fixed [ 1 ]
Status Open [ 1 ] Closed [ 6 ]

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  • Assignee:
    Ian Rogers
    Reporter:
    Ian Rogers
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