Details
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Type:
Improvement
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Status:
Closed
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Priority:
Major
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Resolution: Fixed
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Affects Version/s: None
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Fix Version/s: None
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Component/s: Compiler: Optimizing, Instruction Architecture: Intel
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Labels:None
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Number of attachments :
Description
Currently SSE rules just perform FP math using registers and not memory operands. We should have memory operand rules mirroring those for integer IA32 instructions. We should also look at issues such as conditional moves. The current support for floating point conditional moves is based on what the x87 supports. SSE introduces new instructions which we should possibly adapt the branch optimizations to target.
Issue Links
- is duplicated by
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RVM-359
Introduce two non-terminals called float_load and double_load, and impove the SSE2's add, sub, mul, div rules with the two terminals. The cost of the original add,sub,mul, div rules was changed to match the description of the BURS file.
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The AMD64 optimization guide recomends:
Use the MOVLPS and MOVLPD instructions to move scalar floating-point data into the XMM registers prior to addition, multiplication, or other scalar instructions.
this is because it avoids clearing the upper 64 or 96 bits of the register. Currentyly we use MOVSS and MOVSD.
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25112.PDF page 212